Static timing analysis (STA) checks whether every path in a chip meets its timing budget by adding up worst-case gate and wire delays. It is exhaustive and vector-less: every path is covered at once, with no test inputs, in seconds instead of the hours a SPICE simulation would need. That is why STA, not simulation, signs off timing on real designs.
Si-Time analyses conventional clock-based designs with the same NLDM and CCS timing models and SDC constraints used in today’s sign-off flows, so adopting it changes nothing about how your team already works. It also analyses asynchronous circuits, which have no global clock, and designs that mix both styles, including latches and circuits with loops.
Where paths fail, Si-Time goes beyond reporting. In-place timing optimisations fix violations directly, and the updated netlist and/or DEF goes straight back into your flow.
Key capabilities:
Call to action: Request a demo → Contact us
Copyright © 2023 Silicon Highway (SiHi) Technologies, All rights reserved. Designed & Created by Onum Group
