Radiation-aware layouts, analysed and hardened at gate level

In space, electronics are exposed to high-energy particles that can cause bit flips, degradation or permanent damage. One common effect is the Single Event Transient (SET): a particle strike creates a short voltage pulse that travels through the logic and can be captured as a wrong value. Ensuring radiation tolerance improves mission reliability, prevents costly failures and supports long-term operation in orbit or deep space.

Si-Space finds the vulnerable parts of a design during implementation, not after tape-out. Its SET propagation engine uses advanced timing and wire models, calibrated for technologies down to 2 nm and evaluated for accuracy and speed-up against SPICE. This makes it fast enough to analyse large designs.

Si-Space then hardens the design in a closed optimisation loop. It applies gate-level mitigation techniques, re-analyses the result and balances hardening against timing and area overhead. The output is a hardened netlist and DEF, so you avoid expensive redesigns and mission delays.

Key capabilities:

  • SET analysis of a given layout under user-defined particle profiles and scenarios
  • Identification of sensitive cells and nets [confirm]
  • TMR-aware spacing: places redundant copies far enough apart for your radiation profile
  • Automatic application of mitigation techniques to the DEF [confirm which techniques to name]
  • Works on your existing synthesised netlist and physical data

Who it’s for: space and satellite electronics, aviation, automotive safety, high-energy physics and medical designs.

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