Si-Space identifies the vulnerable parts of a design during physical implementation, not after tape-out and neither at RTL level where several parts of the design are optimized. Its SET propagation engine uses advanced timing and wire models, calibrated for technologies down to 2 nm and evaluated for accuracy and speed-up against SPICE. As a result, Si-Space is capable of analyzing large designs in an exhaustive and vector–less manner. 

Using the information obtained during the radiation sensitivity analysis, Si-Space can harden the design in a closed optimization loop. It applies gate-level mitigation techniques, re-analyses the result and balances hardening against timing and area overhead. The output is a hardened netlist and DEF file, avoiding expensive redesigns and mission delays. 

Key capabilities: 

• Works on your existing synthesized netlist and physical implementation data 

• SET and SEU analysis of a given layout under user-defined particle profiles and scenarios 

• Identification of sensitive cells, nets and Flip Flops 

• Automatic application of mitigation techniques to the DEF such as TMR, gate resizing and charge sharing among others 
• TMR-aware spacing: automatically groups and places redundant copies with enough spacing based on a particle profile, avoiding multi-bit upsets on the TMR FFs.