Si-Place brings floorplanning, clustering, global placement, legalisation and detailed placement together in one physical design infrastructure. It reads industrial formats (Verilog, LEF, Liberty, DEF) and handles large designs while keeping their netlist hierarchy.

The result is a legal, optimised placement written as DEF, ready for clock tree synthesis and routing. Timing-driven placement, macro and datapath support, and ECO commands give you control over the result.

How it works:

1. Floorplanning: handles large designs with their physical (netlist) hierarchy.
2. Clustering and partitioning: divide-and-conquer placement, grouping placement objects into clusters.
3. Global placement: spreads the cells to minimise wirelength, delay and overlap.
4. Legalisation: removes the remaining overlaps while disturbing the solution as little as possible.
5. Detailed placement: a final optimisation step that further reduces wirelength, delay and overlap.
    

Key capabilities:

• Placement of synthesised gate-level netlists
• Starts from scratch or from an existing floorplan / DEF
• Constraint-aware, using SDC timing constraints
• Legalisation to the placement rows and site grid
• Placement quality reports [confirm: e.g. wirelength, density, timing]