Si-Part – SiHi Tech

Split large designs into balanced, manageable partitions

Si-Part provides the capability to seamlessly divide and conquer large gate-level netlists to a preset number of physical design partitions. These partitions may be extracted as a multi-level hierarchical netlist and be used for Block based design. It plays a crucial role in the design flow of complex integrated circuits, helping designers manage design complexity, optimize performance, and achieve faster time-to-market for semiconductor products.

Large designs are easier to implement, verify and reuse when they are split into well-defined blocks. Si-Part reads your synthesised gate-level netlist, and optionally its physical data, and partitions the circuit according to your constraints. It then exports a new hierarchical netlist ready for the next steps of your flow, together with statistics for each partition.

Key capabilities:

Gate-level netlist-to-netlist partitioning
User-defined partition constraints [confirm: e.g. number of partitions, size balance, cut limits]
Optional use of physical data (DEF, LEF) for layout-aware partitioning
Export of a new hierarchical netlist
Per-partition statistics: cell count, area, cut nets [confirm which statistics are reported]

Typical uses: hierarchical implementation of large SoCs, multi-die or chiplet splitting [confirm], parallel implementation by several teams.

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Split large designs into balanced, manageable partitions

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